ENGINEERING BUILD / ACTIVE DEVELOPMENT SOURCE BUILD · HOSTED SERVICES NOT ACTIVE

01 / RSPICE WORKBENCH / ANALOG · MIXED-SIGNAL · RF

Circuit simulation built around an inspectable run record.

RSpice joins SPICE-compatible netlist elaboration, nonlinear and complex sparse solving, compact models, verification, and four local interfaces in one Rust workspace. The current Workbench design below is rendered as HTML at 1440 × 900 and scales to the available viewport.

REAL SOLVE: KLU-class sparse path
COMPLEX SOLVE: faer / AC families
HOSTS: Desktop / CLI / Python / WASM

Open WASM lab Search technical reference

SOURCE REVISION: c216a0922ae3
WORKSPACE: v0.1.0 / Rust 1.94
NIGHTLY GATE: 113 ngspice decks configured
RETAINED CORPUS: 2123 Xyce contracts
HOSTED STATE: Identity / sync / compute not active

Hierarchy, schematic capture, checks, run controls, and property inspection in the current Workbench design. This frame renders HTML at its source dimensions; it is not the released egui application.FIG. 01 / GUI MOCKUP

02 / SYSTEM ARCHITECTURE

One run moves through explicit, inspectable stages.

RSpice does not treat a simulation as a plot disconnected from its inputs. The parsed deck, elaborated hierarchy, selected model implementations, solver controls, status, measurements, and exported datasets form one run contract.

RUN PIPELINE / NATIVE COREINPUT IDENTITY RETAINED THROUGH EXPORT

01PARSE

Deck & directives

Cards, expressions, analysis order, saves, measures, includes, and libraries.

02ELABORATE

Resolved design

Flattened subcircuits, evaluated parameters, model sections, and instance graph.

03ASSEMBLE

MNA systems

Real or complex sparse matrices, device state, sources, and analysis-specific stamps.

04SOLVE

Analysis family

Continuation, Newton, transient integration, sweeps, or frequency-domain execution.

05QUALIFY

Result record

Status, measurements, comparison evidence, provenance, and machine-readable output.

ENGINE CONTRACTrspice-core

NETLIST: .SUBCKT, .PARAM, expressions, .INCLUDE, .LIB, .OPTIONS, .TEMP
REAL PATH: In-tree KLU-class sparse factorization for nonlinear and time-domain systems
COMPLEX PATH: faer-backed sparse solves for AC and related complex analysis families
PARALLELISM: Rayon across AC sweeps, Monte Carlo runs, and configured process-corner workers
FAILURE MODEL: Typed parse, topology, convergence, non-finite, timeout, verification, and I/O outcomes

HOSTEXECUTIONPRIMARY USESTATE

DesktopNative / egui / wgpu

Schematic capture, local projects, analysis configuration, and waveform inspection.

SOURCE BUILD

CLINative / batch

Deck execution, reports, conversion, comparison, time budgets, and CI gating.

SOURCE BUILD

PythonPyO3 / NumPy

Programmatic DC, transient, and AC results inside numerical workflows.

SOURCE BUILD

BrowserWASM / single thread

Netlist summaries plus selected DC, AC, and transient result snapshots.

EXPERIMENTAL

Hosted runnerManaged service

Planned queued sweeps, retained artifacts, organization policy, and result links.

NOT ACTIVE

03 / SOLVER & RUN RECORD

Inputs, solver status, and verification output stay linked.

RUN CONTENTSNETLIST → ELABORATION → ANALYSIS → OUTPUTSERIALIZABLE RECORD

A1 / ELABORATED INPUT

Resolved deck and model graph

The run records parsed cards, evaluated parameters, flattened subcircuits, include paths, model selection, and the generated netlist used for assembly.

SPICE-compatible decks
Model and include provenance
Inspectable generated netlist

A2 / EXECUTION STATUS

Typed solver outcomes

Unsupported model physics, invalid cards, non-convergence, non-finite values, comparison failures, and timeouts return distinct statuses.

Explicit rejection paths
Watchdog-aware execution
Machine-readable reports

A3 / VERIFICATION OUTPUT

Measurements and comparison artifacts

Measurements, golden-reference differences, random seeds, solver options, model identity, and build information remain attached to exported results.

JUnit and TAP reporting
Golden comparison
Input-linked result summary

MODIFIED NODAL ANALYSISDAMPED NEWTONADAPTIVE TRANSIENTSPARSE REAL + COMPLEX PATHSRAYON PARALLEL FAMILIES

SOLVER SUBSYSTEMS

Numerical controls exposed as engineering decisions.

The engine distinguishes convergence aids, matrix backends, integration policy, reproducibility, and termination conditions instead of reducing every failure to “simulation failed.”

DC EQUILIBRIUM

Damped Newton with continuation

Merit-based line search, model-aware limiting, gmin stepping, source stepping, and pseudo-transient continuation establish the nonlinear operating state.

CONTROL: --maxiter / --gmin
PRESETS: fast / default / robust

REAL SPARSE PATH

KLU-class factorization

The in-tree sparse path handles real-valued MNA systems for operating point, sweeps, and transient steps without routing through a dense fallback.

CHECKS: pivot / residual / finite
OUTCOME: typed singularity or solve status

COMPLEX SPARSE PATH

faer-backed AC systems

Complex small-signal systems retain magnitude and phase for AC-family results, noise, transfer, and frequency-domain extraction.

FAMILIES: AC / NOISE / PZ / RF paths
SWEEP: frequency points parallelizable

TIME INTEGRATION

Adaptive LTE-controlled transient

Trap, Gear, automatic trap/Gear, and Euler modes operate under minimum and maximum step bounds, truncation error control, source breakpoints, and safe cancellation points.

CONTROL: --trtol / min / max step
STATE: checkpoint / exact-deck resume

PARALLEL FAMILIES

Deterministic independent work

AC points, Monte Carlo samples, and configured corner workers use Rayon where runs can be separated without sharing mutable solver state.

MC: seed-stable sampling
CORNERS: collision-free tagged outputs

TERMINATION

Failure states survive export

Parse, topology, convergence, non-finite, timeout, interruption, measurement, comparison, configuration, and I/O outcomes remain distinguishable to callers and CI.

TIMEOUT: exit 124
VERIFY: exit 3

04 / ANALYSIS MAP

Implemented analyses and current exposure.

Core analyses run through the native engine. Selected statistical, periodic, and RF paths use deck, CLI, or IDE-specific entry points; the status column distinguishes complete paths from partial kernels.

REPRESENTATIVE RESPONSE FAMILIESDC · TRAN · AC

FAMILYCOMMAND / ROUTEENGINE BEHAVIORSTATUS

01

Operating point & sweeps

.OP .DC .STEP .TEMP .TF .SENS

Solves the nonlinear bias state, including nested two-source DC sweeps, temperature and parameter families, transfer functions, and small-signal sensitivity.CORE

02

Transient & spectral

.TRAN .FOUR THD IMD

LTE-controlled adaptive timestepping with checkpoint/resume segmentation, followed by Fourier, distortion, eye-diagram, and jitter post-processing paths.CORE

03

Linear frequency domain

.AC .NOISE .PZ

Complex small-signal sweeps, input/output-referred noise, and pole-zero extraction over the elaborated device and model graph.CORE

04

Measurement & verification

.MEAS GOAL TOL COMPARE

Measures TRAN, DC, AC, and NOISE results; gates runs against tolerances; compares golden data; and emits machine-readable pass/fail reports.CORE

05

Statistical & corners

.MC --monte-carlo --corners

Runs seeded operating-point parameter variation and process-corner campaigns. Exposure currently spans selected deck, CLI, and IDE entry points.SELECTED

06

Periodic & RF

PSS HB .STB S-PARAM

Includes shooting PSS, harmonic balance, stability, and two-port S-parameter paths with Touchstone export. Availability is analysis- and interface-specific.SELECTED

07

Advanced analysis boundary

PAC PNOISE PXF PSTB ENV .DISTO

Conversion-matrix, monodromy, envelope, and multirate mathematics exist below the product layer. They do not yet have complete circuit extraction; .DISTO currently maps to AC rather than a Volterra engine.KERNEL / PARTIAL

IMPLEMENTED DEVICE, DECK, AND HOST FEATURES

DEVICE → DECK → SOLVE → EXPORT

01 / SEMICONDUCTOR MODELS

MOS and bipolar models

Native models cover the principal silicon paths; bundled Verilog-A sources provide generated implementations for additional compact-model families.

BSIM4 v4.8, BSIM3v3.3, VDMOS, EKV3, MOS1/2/3/6, BSIM1/2
Generated BSIM-SOI and EKV 2.6 built-ins where sources are bundled
Gummel-Poon plus generated VBIC, HICUM, and MEXTRAM where sources are bundled

02 / DEVICES & INTERCONNECT

Junction, magnetic, and line devices

Device registration includes junction models, magnetic components, and ideal or lossy transmission-line elements.

Diode, JFET/JFET2, MES/MESA/HFET families, and GaN HEMT
Temperature-aware R/C/L, coupled and multi-winding transformers
Jiles–Atherton saturable inductors; ideal, LTRA, TXL, and CPL lines

03 / SOURCES & MIXED SIGNAL

Sources, controlled elements, and bridges

Independent and controlled sources provide time-domain stimulus, behavioral expressions, switching, and analog/digital conversion.

PULSE, SIN, EXP, PWL, SFFM, AM, TRNOISE, and PWL file sources
E/F/G/H controlled and B behavioral sources; controlled switches
XSPICE-style analog/digital elements, tri-state drivers, and A/D–D/A bridges

04 / DECK & MODEL PIPELINE

Netlist elaboration and Verilog-A

The parser resolves parameters, includes, libraries, and subcircuits before matrix assembly; Verilog-A uses interpreted, JIT, and generated-Rust paths.

.SUBCKT, .PARAM, expressions, .INCLUDE, and .LIB
.OPTIONS, .TEMP, engineering suffixes, and flattened elaboration
Verilog-A parser, semantic IR, bytecode VM, native JIT, and generated-Rust backends

05 / AUTOMATION & VALIDATION

CLI reports and regression tests

CLI exit codes and report formats allow measurement failures, timeouts, invalid results, and golden-reference mismatches to stop CI jobs.

run, info, check, compare, convert, and compile-va
Typed exit codes, timeouts, JUnit, TAP, JSON summaries, and measurement files
ngspice and Xyce corpus harnesses with explicit oracles and failure tracking

06 / INTERFACES & DATA

Desktop, Python, WASM, and formats

The egui application, CLI, Python bindings, and WebAssembly bindings use the same core, with target-specific analysis exposure.

egui/wgpu desktop Workbench, CLI, Python/NumPy, and WebAssembly bindings
SPICE RAW, ASCII RAW, CSV, TSV, JSON, HDF5, and Touchstone output
Native desktop is the primary target; browser support is experimental and mobile UI remains a design target

Read the revision-specific technical scope and limitations

05 / DEVICE & MODEL SYSTEM

Model coverage includes an explicit physics boundary.

Native device implementations and generated Verilog-A devices share the simulator, but they are not presented as interchangeable black boxes. Requested modes that are not implemented are rejected with typed errors rather than silently approximated.

FAMILYIMPLEMENTATIONCURRENT COVERAGEBOUNDARY

M

MOSFET

Native + generated

BSIM4 v4.8, BSIM3v3.3, VDMOS, EKV3, MOS1/2/3/6, legacy BSIM1/2; generated BSIM-SOI and EKV 2.6 where bundled sources are available.

Unsupported levels and unported mode selectors fail explicitly.

Q

Bipolar

Native + generated

Gummel-Poon BJT plus generated VBIC, HICUM, and MEXTRAM implementations where redistributable Verilog-A sources are bundled.

Generated devices are canonical when their source package is enabled.

D/J/Z

Junction & HEMT

Native

Diode, JFET level 1, Parker-Skellern JFET2, an internal Xyce JFET2 compatibility mode, MES/MESA/HFET-family devices, and a physics-style GaN HEMT path.

CMC ASM-HEMT and MVSG qualification remains future work.

R/C/L/K

Passive & magnetic

Native

Temperature-aware resistance, capacitance, and inductance; coupled and multi-winding transformers; Jiles–Atherton saturable-inductor hysteresis.

State and history participate in transient checkpointing.

T/O/P

Interconnect

Native

Ideal lines, LTRA and TXL lossy paths, and CPL coupled transmission-line elements for time- and frequency-domain use.

Analysis availability follows each registered device path.

A/X

Mixed signal

Native compatibility

XSPICE-style analog/digital elements, tri-state drivers, controlled switches, behavioral sources, and A/D–D/A bridges.

Digital/event surface maturity varies by element.

VA

Verilog-A

Compiler pipeline

Parser, semantic analysis, canonical IR, bytecode VM, x64-first native JIT, and a generated-Rust backend for feature-gated built-ins.

Native JIT requests either construct fully or return a typed error.

VERILOG-A PRODUCT PATHSOURCE-OWNED MODEL IDENTITY

Model source

External module or bundled CMC package with its original source identity.

Semantic IR

Parsed disciplines, parameters, branches, contributions, and typed expressions.

Execution backend

Bytecode VM, requested native JIT, or generated Rust for bundled built-ins.

Registered device

Explicit model level, parameter schema, runtime state, and analysis stamps.

Qualification

Focused tests, oracle replay, corpus decks, and typed unsupported behavior.

FAIL-CLOSED MODEL POLICY

For example, a BSIM4 card that requests unported gate/body resistance networks, NQS behavior, material modes, or unsupported mode selectors is rejected. A plausible current from incomplete physics is not treated as a successful simulation.

Search the generated device reference

06 / ENGINEERING WORKFLOW

The Workbench design spans design entry through review evidence.

The workflow below describes the current HTML Workbench redesign rendered at the top of this page. The native egui application and simulation engine already exist; this redesigned shell is a design target, not a claim that every panel is released.

WORKBENCH INFORMATION ARCHITECTUREDESKTOP-FIRST / RESPONSIVE TARGETGUI REDESIGN

01

Project, hierarchy, and schematic

SOURCE + DESIGN

Project files, cell hierarchy, symbols, instances, nets, ports, parameters, model references, and generated netlists stay navigable from the same design context.

Hierarchy and net navigation
Component shelf and property inspector
Connectivity and annotation checks
Source-to-netlist traceability

02

Analysis plan and run set

GUI REDESIGN

Analyses, PVT dimensions, corners, parameter sweeps, seeds, solver policy, outputs, and qualification checks form a versioned simulation plan rather than a transient dialog state.

Analysis-specific advanced options
Corner and temperature matrix
Resource and parallel-worker policy
Preflight checks before execution

03

Jobs, targets, and diagnostics

ENGINE + DESIGN

Local runs and planned remote jobs expose queued, running, completed, cancelled, timed-out, failed, and verification-blocked states with retained diagnostics.

Per-task run-set progress
Stop at safe solver boundaries
Residual and convergence history
Input and build fingerprint

04

Datasets and visualizations

SOURCE + DESIGN

Waveforms, spectra, measurements, tables, overlays, and exported datasets remain scoped to an immutable result manifest so a viewer cannot silently combine incompatible runs.

Time, frequency, XY, eye, and statistical views
A/B cursors and derived expressions
Dataset comparison and export
Result provenance in the inspector

05

Verification and sign-off evidence

GUI REDESIGN

Specification matrices, corner coverage, regression comparisons, model qualification, reliability checks, review comments, and approvals are represented as evidence attached to a run.

Requirements-to-measurement mapping
Pass, fail, not evaluated, and blocked
Golden reference differences
Report and audit export

06

Automation and reproducibility

SOURCE BUILD

CLI, Python, reports, deterministic seeds, checkpoints, output conversion, and explicit exit codes let the same engineering checks operate outside the graphical client.

JUnit, TAP, JSON, and measurement files
Golden compare and reviewed bless flow
Python/NumPy result access
Shell completions and configuration files

07 / AUTOMATION & DATA

Batch execution is an engineering interface, not a secondary export path.

The CLI executes deck analyses in declared order, reports measurements, enforces time budgets, distinguishes verification failures from simulator failures, and writes analysis-shaped datasets for downstream tools.

CI RUN / MEASUREMENT GATEEXIT STATUS IS PART OF THE CONTRACT

$ rspice run afe.sp \
    --corners tt,ss,ff \
    --corner-lib pdk/corners.lib \
    --timeout 600 \
    --meas --meas-format json \
    --report-format junit \
    --report-file results.xml \
    --summary run-summary.json

TRAN   accepted  1,053 points
MEAS   vpeak     4.999773e+00  PASS
MEAS   risetime  2.197215e-04  PASS
RUN    3 corners / 0 failed
EXIT   0

CODECLASSMEANING

0SUCCESS

Simulation ran and every configured check passed.

1SIMULATION

Convergence, non-finite, Verilog-A compile, or conversion failure.

3VERIFICATION

A measurement failed or could not evaluate, or golden comparison mismatched.

65INPUT

Netlist parse failure or singular topology found by checking.

124TIME BUDGET

Run exceeded --timeout and stopped at a safe point.

130INTERRUPTED

Ctrl-C requested controlled termination.

All commands, flags, and exit codes

RESULT FORMATS

RAW / ASCII / CSV / TSV / JSON / HDF5

Multi-analysis decks receive tagged outputs. Table-shaped TF, pole-zero, and sensitivity results use compatible formats rather than being forced into an unsuitable HDF5 section.

RF DATA

Complex tables / Touchstone

Two-port extraction writes S11, S21, S12, and S22 across the deck’s AC sweep, with .s2p output when Touchstone is selected.

REPORTS

JUnit / TAP / JSON summary

Tool version, per-run status, measurements, written files, and the overall verdict can be consumed without parsing terminal prose.

PYTHON

PyO3 / NumPy arrays

DC, transient, and AC result data can be returned directly to Python for numerical analysis, regression work, and custom plotting.

WEBASSEMBLY

JSON-serializable snapshots

The experimental single-threaded browser binding exposes netlist summaries and selected DC, AC, and transient execution without a hosted upload.

REPRODUCIBILITY

Seeds / fingerprints / checkpoints

Monte Carlo defaults to a deterministic seed; transient resume requires a byte-identical deck fingerprint; outputs retain run configuration and model identity.

08 / VALIDATION EVIDENCE

Configured gates, retained corpora, and raw files stay separate from pass claims.

The public validation page is regenerated from the exact RSpice source commit. A CI conclusion is shown only when the downloaded artifact names that same commit; otherwise the site reports configuration and inventories without inventing a pass percentage.

SOURCEc216a0922ae3

Commit used for the generated reference and validation inventory.

NIGHTLY RATCHET113 decks

Configured aggregate; no more than 2 failing decks.

NGSPICE MANIFEST49 entries

Numeric, smoke, locked-grid, measure, scripted, and expected-unsolvable modes.

XYCE MANIFEST2123 contracts

Retained deck and wrapper requirements, not a claim of successful execution.

Unit & integration

Parser, expressions, device equations, assembly, solvers, analyses, formats, and interface errors.

Oracle replay

Retained inputs and outputs for history-coupled devices and numerical state transitions.

ngspice corpus

Deck-by-deck execution with probe-aware floors, relative tolerance, watchdogs, and explicit aggregate output.

Xyce contracts

Runtime decks plus retained wrapper requirements that remain visible until the harness implements them.

Benchmark context

Source-controlled host, executable paths, repeats, deck names, medians, and raw scoreboard JSON.

Open revision-pinned validation Inspect catalog JSON Read comparison methodology

09 / AVAILABILITY

Current availability by host and service.

Source code, the experimental browser path, the Workbench mockup, and planned hosted services are separate deliverables with different availability.

AVAILABILITY MATRIXCURRENT PUBLIC STATUSCHECK THE SOURCE REVISION

STATUSCOMPONENTCURRENT SCOPEDETAIL

SOURCE BUILD

Native engine & tools

The Rust engine, CLI, Python bindings, validation harnesses, and desktop egui application are present in the public source tree.

Build from source

SOURCE BUILD

Verilog-A toolchain

Parser, semantic IR, bytecode VM, x64-first JIT, standalone compilation, and generated-Rust built-in paths are present behind their applicable features.

Inspect compiler surface

EXPERIMENTAL

WebAssembly & browser IDE

The WASM interface exposes netlist summaries plus DC, AC, and transient runs; WebGPU and single-thread limits apply.

Open WASM lab

MOCKUP

New Workbench UI

The embedded desktop, tablet, and phone layouts are HTML design mockups, not the current egui application.

Inspect mockup

GENERATED

Reference & validation status

The catalog, gate configuration, manifest counts, benchmark context, and raw files are generated from the source commit named on each page.

Open generated status

ROADMAP

Accounts, sync, cloud & sharing

Live collaboration, cloud saves, managed simulation, and published circuit URLs are planned services; they are not live.

View hosted plan

10 / HOSTED SERVICES

Local projects remain usable without hosted services.

Planned services add identity, project synchronization, collaboration, managed simulation, and public or private result links. Local files and local simulation remain independent of those services.

01 / NOW

Local project

Files, models, engine, and results stay on the engineer’s device.

02 / PLANNED

Identity boundary

Authentication belongs to the future application service, not the public website.

03 / PLANNED

Versioned projects

File revisions, permissions, presence, comments, and public, unlisted, or private sharing.

04 / PLANNED

Managed simulation

Queued runs, runner selection, cost estimates, retained outputs, and shareable result URLs.

ACCOUNT LOCATION

Accounts belong to the application service.

The public site remains account-free. Registration, organization management, billing, and authenticated project access will use the hosted application.

SHARING POLICY

Every shared URL includes visibility controls.

Planned result pages distinguish public, unlisted, and private access and retain the input revision, run configuration, expiration, revocation, and export settings.

COMPUTE BILLING

Runner time and storage are separate usage.

Local simulation does not require a hosted plan. Managed corner, Monte Carlo, and optimization jobs show estimated runner and storage cost before submission.

SERVICEPLANNED CONTRACTDATA BOUNDARYCURRENT STATE

Identity & organizations

Registration, SSO options, organization membership, editor/reviewer roles, seat assignment, and billing ownership.

Hosted identity and policy data; no circuit upload required for a local license.NOT ACTIVE

Cloud project saves

Versioned files, model references, project revisions, restore points, branch/merge policy, and per-project retention.

Opt-in project content encrypted in transit and at rest; local-only projects remain local.NOT ACTIVE

Live collaboration

Presence, selections, comments, review threads, edit conflict handling, and an auditable history tied to project revisions.

Only authorized project members and invited reviewers; role-controlled write access.NOT ACTIVE

Managed simulation

Preflight, runner class, queue state, resource estimate, cancellation, logs, retained datasets, and downloadable artifacts.

Submitted run package and selected model dependencies; private-runner option planned for controlled environments.NOT ACTIVE

Published circuits & results

Proposed short URLs for a circuit, frozen result, report, or interactive viewer with public, unlisted, private, expiring, and revocable visibility.

A publication is a deliberate copy with its own visibility and revision, not an implicit exposure of the source project.NOT ACTIVE

Governance & audit

Organization policy, SSO enforcement, export controls, audit records, retention policy, support bundles, and administrative exports.

Enterprise control plane; private runner and offline licensing remain separate deployment choices.NOT ACTIVE

LOCAL PRODUCT

Files and simulation do not depend on an RSpice account.

Native desktop, CLI, Python, local model libraries, and local result export remain usable when hosted services are unavailable or intentionally disabled.

CONNECTED PRODUCT

Accounts belong where authenticated project state lives.

The future application service—not this public site—owns registration, sessions, organization policy, billing, collaboration, managed jobs, and shared URLs.

11 / LICENSING PLAN

Proposed seat licenses and hosted-compute billing.

These prices are planning assumptions, not active offers. Commercial editing uses named seats; view-only review is free; managed runner time and storage are billed separately.

EVALUATION / ACADEMIC

Evaluation

$0source and non-commercial preview

Source-built local engine, CLI, and desktop tools
Experimental browser preview
Personal, educational, and evaluation use
No hosted storage or managed compute included
Community issue tracking; no response SLA

Build from source

COMMERCIAL

Professional

$149named user / month, billed annually

Commercial native license at launch
Desktop, CLI, Python, and CI workflows
Local projects and local simulation without cloud dependency
Version updates and standard technical support
Optional metered managed compute after service launch

Describe an evaluation

COLLABORATIVE

Team

$249editor / month, billed annually

Professional license plus hosted project editing after launch
Versioned saves, roles, comments, review, and audit history
View-only reviewers stay free
Included monthly hosted-service allowance proposed
Managed compute billed beyond included allowance

Describe an evaluation

CONTROLLED ENVIRONMENTS

Enterprise

Customannual commitment

Offline, floating, and private-runner plans
SSO, organization policy, retention, and audit export
Vendor security and deployment review
Qualification assistance and negotiated support terms
Annual minimum with volume and multi-year pricing

Describe requirements

No account, payment flow, cloud storage, managed compute, or subscription checkout is active on this site today. Any hosted compute will be billed separately from seats.

SEAT REVENUE

Annual named-user licenses

Professional and Team prices are shown as monthly equivalents but billed annually. This supports predictable engineering budgets and recurring product development.

REVIEW ACCESS

Free viewers, paid editors

Stakeholders can inspect and comment without consuming an editor seat; users who modify projects, plans, or organization policy require a paid seat.

USAGE REVENUE

Compute and retained storage

Hosted runner class, wall time, memory tier, retained artifact volume, and storage duration are metered separately with an estimate before submission.

ENTERPRISE REVENUE

Control-plane and support terms

Offline activation, floating entitlement, SSO, private runners, audit export, deployment review, and response commitments sit behind an annual minimum.

SOURCE / BROWSER EVALUATION

Build the CLI or run the experimental WASM path.

Open WASM lab Prepare an evaluation inquiry