RSPICE / GENERATED REFERENCE
Search the source-defined analysis, model, CLI, and interface catalog.
Generated from commit 1efe7d9541f8. The checked-in snapshot is regenerated during site builds and compared in CI.
- SOURCE REVISION
- 1efe7d9541f8
- COMMIT DATE
- 2026-07-20
- WORKSPACE VERSION
- 0.1.0
- RUST VERSION
- 1.94
CATALOG SEARCH
Filter 128 generated entries.
128 entries shown
01 / ANALYSES
Analysis families
| DOMAIN | ANALYSES |
|---|---|
| Operating point & sweeps | .OP, .DC (including two-source sweeps), temperature sweeps, .STEP |
| Time domain | .TRAN, with LTE-controlled adaptive timestepping and checkpoint/resume segmentation |
| Small-signal | .AC, .NOISE, .PZ, .TF, .SENS, third-order Volterra .DISTO (harmonic and two-tone intermodulation) |
| Statistical | Operating-point Monte Carlo parameter variation, process corners |
| Periodic / RF | Periodic steady state (shooting), harmonic balance, two-port S-parameters with Touchstone export |
| Post-processing | .MEAS over TRAN/DC/AC/NOISE with GOAL/TOL pass-fail gating, .FOUR; THD/IMD, eye-diagram, and jitter metrics |
02 / DEVICES
Device and compact-model families
| FAMILY | MODELS |
|---|---|
| MOSFET | Native BSIM4 v4.8 (LEVEL=14/54, canonical mode set), BSIM3v3.3 (LEVEL=8/9/49, CAPMOD=2/3), VDMOS, EKV3, Berkeley MOS1/MOS2/MOS3/MOS6, and legacy BSIM1/BSIM2; generated Verilog-A builtins are canonical for BSIM-SOI (LEVEL=10/55/56/57) and EKV 2.6 (LEVEL=260); unsupported MOS levels fail closed until generated or native support and validation are added |
| Bipolar | Gummel-Poon BJT (default / LEVEL=1) plus generated Verilog-A builtins for VBIC (LEVEL=4/9/11/12/13), HICUM, and MEXTRAM where bundled sources are available; unsupported advanced BJT levels fail explicitly until generated support lands |
| Junction | Diode, JFET level 1 and native Parker-Skellern JFET2 (NJF/PJF LEVEL=2, default/best-available), an internal Xyce modified-Shockley JFET2 compatibility mode, MES/MESA/HFET-family Z devices, GaN HEMT |
| Passives | R / C / L with temperature coefficients, coupled inductors and multi-winding transformers, saturable inductor (Jiles–Atherton hysteresis) |
| Transmission lines | Ideal, lossy (LTRA, TXL), coupled (CPL) |
| Sources | Independent V/I with PULSE, SIN, EXP, PWL, SFFM, AM, and TRNOISE white + 1/f waveforms; E/F/G/H controlled sources; B behavioral sources; PWL file sources |
| Switches & macromodels | Voltage- and current-controlled switches, op-amp macromodel |
| Mixed-signal | XSPICE-style analog/digital elements, tri-state drivers, A/D–D/A bridges |
| Verilog-A | Compiled behavioral modules (below) |
03 / CLI COMMANDS
Top-level commands
| COMMAND | DESCRIPTION |
|---|---|
rspice run | Execute simulations |
rspice health | Probe process liveness or parser-to-solver readiness |
rspice info | Print parsed netlist information |
rspice check | Validate syntax and connectivity |
rspice compare | Compare output against a golden result |
rspice convert | Convert between RAW, ASCII RAW, CSV, JSON, TSV, and HDF5 |
rspice compile-va | Compile Verilog-A models |
rspice completions | Generate shell completion scripts |
04 / CLI OPTIONS
Command options, configuration, and exit codes
RSpice CLI / Commands / rspice run — Execute Simulations / Output options8 entries
| Flag | Description |
|---|---|
| -o, --output <FILE> | Output file for results. With several analysis cards in one deck, each analysis writes its own tagged file: out.csv → out.op.csv, out.tran.csv, ... |
| -f, --format <FORMAT> | Output format: raw, ascii, csv, json, tsv, hdf5 (default: config output.format, else raw) |
| --save <SIGNAL> | Limit exported signals, replacing the netlist .SAVE/.PROBE selection: V(out), V(a,b), I(v1), @m1[id], all (repeatable) |
| --meas | Print .MEAS measurement results |
| --summary <FILE> | Write a versioned JSON run summary — build/run identity, execution counts and timing, effective resource limits, typed failures, every measurement, result files, and overall verdict — to FILE, or stdout with - |
| --progress | Show a live percentage bar during transient analysis (the engine reports its completed fraction) |
| --compress | Enable waveform compression for long simulations |
| --compress-tol <TOL> | Compression tolerance (default: config compressiontolerance, else 1e-4; requires --compress) |
RSpice CLI / Commands / rspice run — Execute Simulations / Run-discipline options6 entries
| Flag | Description |
|---|---|
| --timeout <SECONDS> | Abort the run after this budget; exits 124. Transient and DC sweeps stop at the next safe point. Ctrl-C stops the same way and exits 130 |
| --allow-failed-meas | Exit 0 even when .MEAS measurements fail (default: exit 3) |
| --allow-nonfinite | Export results containing NaN/Inf instead of failing (default: simulation error) |
| --checkpoint <FILE> | Save the transient integrator state when the run completes, for later --resume |
| --resume <FILE> | Continue a transient from a saved checkpoint; the deck must be byte-identical (fingerprint-checked) and a segmented run reproduces the uninterrupted waveform |
| --tran-stop <TIME> | Override the .TRAN stop time without editing the deck, so checkpoint segments share identical source |
RSpice CLI / Commands / rspice run — Execute Simulations / Simulation options16 entries
| Flag | Description |
|---|---|
| --temp <TEMP> | Override simulation temperature (Celsius) |
| --maxiter <N> | Maximum Newton-Raphson iterations |
| --abstol <TOL> | Absolute convergence tolerance |
| --reltol <TOL> | Relative convergence tolerance |
| --residual-reltol <TOL> | Relative residual tolerance for equation convergence checks |
| --voltage-abstol <TOL> | Voltage absolute tolerance (VNTOL) |
| --current-abstol <TOL> | Current absolute tolerance |
| --charge-abstol <TOL> | Charge absolute tolerance (CHGTOL) |
| --min-step <TIME> | Minimum transient timestep |
| --max-step <TIME> | Maximum transient timestep |
| --integration-method <M> | Transient integrator: trap, gear, trapgear (default), euler |
| --trtol <TOL> | Transient truncation-error tolerance (TRTOL) |
| --gmin <G> | Initial GMIN conductance for convergence aids |
| --convergence <MODE> | DC convergence preset: fast, default, robust |
| -I, --include <DIR> | Add a search directory for .include/.lib references (repeatable) |
| -D, --define <NAME=VALUE> | Override or define a netlist parameter; values accept SPICE suffixes, e.g. -D RLOAD=4.7k (repeatable) |
RSpice CLI / Commands / rspice run — Execute Simulations / Analysis-mode options20 entries
| Flag | Description |
|---|---|
| --monte-carlo <N> | Run N Monte Carlo iterations (operating-point variation); independent runs solve in parallel across cores with seed-stable sampling |
| --seed <SEED> | Random seed for Monte Carlo; the default seed 1 makes runs reproducible (requires --monte-carlo) |
| --mc-distribution <D> | Variation distribution: gaussian (default), uniform, worst-case |
| --mc-spread <S> | Relative spread: sigma for gaussian, tolerance otherwise (default: 0.01) |
| --mc-param <NAME> | Restrict variation to specific parameters (repeatable) |
| --pss-freq <FREQ> | PSS fundamental frequency in Hz |
| --pss-harmonics <N> | Number of PSS harmonics (default: 9) |
| --pss-tstab <TIME> | PSS stabilization time before the shooting method (default: auto) |
| --hb-freq <FREQ> | Harmonic balance fundamental frequency in Hz |
| --hb-harmonics <N> | Number of HB harmonics (default: 9) |
| --pz-input <NODE> | Pole-zero input node (name or index) |
| --pz-output <NODE> | Pole-zero output node (requires --pz-input) |
| --sens-output <NODE> | Sensitivity analysis output node (name or index) |
| --sens-param <PARAM> | Parameter name for sensitivity analysis (requires --sens-output) |
| --sens-value <VALUE> | Nominal parameter value (default: 1.0; requires --sens-param) |
| --sparam <NODES> | Two-port S-parameter extraction over the deck's .AC sweep: four port nodes as "P1+,P1-,P2+,P2-" (use 0 for grounded references). Writes Touchstone when -o ends in .s2p, else the standard complex table formats |
| --sparam-z0 <OHMS> | S-parameter reference impedance (default: 50) |
| --corners <LIST> | Process corners, comma-separated, e.g. tt,ss,ff |
| --corner-lib <FILE> | Library with one .lib <corner> ... .endl section per corner; each corner re-elaborates the deck with its section applied (requires --corners) |
| -j, --jobs <N> | Parallel workers for corner sweeps (default: 1). Corner outputs are tagged per corner so workers never collide; results are byte-identical to a serial sweep |
RSpice CLI / Commands / rspice run — Execute Simulations / Reporting options4 entries
| Flag | Description |
|---|---|
| --report-format <FORMAT> | CI report format: junit, tap |
| --report-file <FILE> | CI report output file (requires --report-format) |
| --meas-format <FORMAT> | Machine-readable .MEAS format: json, csv |
| --meas-file <FILE> | .MEAS output file (defaults to JSON if --meas-format is omitted) |
RSpice CLI / Commands / rspice info — Netlist Information5 entries
| Flag | Description |
|---|---|
| -d, --detailed | Show detailed element information |
| --models | Show model definitions |
| --hierarchy | Show subcircuit hierarchy |
| --params | Show parameter values |
| --json | Output as JSON |
RSpice CLI / Commands / rspice check — Validate Netlist4 entries
| Flag | Description |
|---|---|
| --connectivity | Warn about floating nodes |
| --models | Check for undefined models |
| --strict | Treat warnings as errors |
| --json | Output as JSON |
RSpice CLI / Commands / rspice compare — Golden File Comparison9 entries
| Flag | Description |
|---|---|
| --abstol <TOL> | Absolute tolerance (default: 1e-9) |
| --reltol <TOL> | Relative tolerance (default: 1e-6) |
| --variables <VAR> | Compare specific variables only (repeatable; default: all) |
| --fail-fast | Stop on first difference |
| --json | Output differences as JSON |
| --allow-truncated | Tolerate point-count mismatches and compare the overlap |
| --ignore-missing | Tolerate golden variables missing from the result |
| --bless | Accept the result as the new reference: copies it over the golden file when they differ, or creates the golden file if it does not exist |
| --interpolate | Linearly resample the result onto the golden file's scale, so runs with different time grids compare point-for-point (never extrapolates) |
RSpice CLI / Commands / rspice convert — Format Conversion5 entries
| Flag | Description |
|---|---|
| --to <FORMAT> | Output format (required) |
| --from <FORMAT> | Input format (auto-detected from the extension if omitted) |
| --variables <VAR> | Variables to keep, by full (V(out)) or bare (out) name (repeatable; default: all) |
| --start <VALUE> | Keep points with scale ≥ this time/frequency |
| --stop <VALUE> | Keep points with scale ≤ this time/frequency |
RSpice CLI / Commands / rspice compile-va — Compile Verilog-A5 entries
| Flag | Description |
|---|---|
| -o, --output <FILE> | Write a JSON interface summary: model name, terminals, internal node count, parameters with defaults and bounds |
| -I, --include <DIR> | Add an include directory (repeatable) |
| --strict | Enable strict LRM compliance mode |
| --detailed | Show detailed compilation information |
| --show-usage | Generate a usage example in the output |
RSpice CLI / Configuration File5 entries
| Variable | Effect |
|---|---|
| RSPICETEMPERATURE | Default simulation temperature (Celsius) |
| RSPICEOUTPUTFORMAT | Default output format |
| RSPICEINCLUDEPATH | Include search paths, platform path separator (; on Windows, : elsewhere) |
| RSPICELIBRARYPATH | Model library paths, platform path separator |
| RSPICEMAX<RESOURCE> | Override any [resources] key in uppercase, for example RSPICEMAXBATCHRUNS or RSPICEMAXNETLISTBYTES |
RSpice CLI / Exit Codes11 entries
| Code | Meaning |
|---|---|
| 0 | Success: simulation ran and every check passed |
| 1 | Simulation error (convergence failure, non-finite results, Verilog-A compile failure, conversion failure) |
| 2 | Usage error (invalid arguments) |
| 3 | Verification failure: a .MEAS failed or did not evaluate, or compare found mismatches |
| 65 | Input format error (netlist parse failure, singular topology from check) |
| 66 | Input file not found |
| 70 | Internal error |
| 74 | I/O error (failed to read input or write output) |
| 78 | Configuration error |
| 124 | Run exceeded --timeout |
| 130 | Interrupted (Ctrl-C) |
05 / WORKSPACE
Rust packages and interfaces
| CRATE | PURPOSE |
|---|---|
rspice-core | Simulation engine: device models, analyses, netlist parser, validation harnesses |
rspice-cli | Command-line interface for simulation, validation, conversion, and reporting |
rspice-ui | Desktop application for schematic editing and waveform inspection |
rspice-veriloga | Verilog-A parser, semantic pipeline, bytecode VM/native JIT runtime, generated-Rust backend |
rspice-python | Python bindings built with PyO3 |
rspice-wasm | WebAssembly bindings for the simulation engine |
rspice-bench | Whole-process benchmark rig against local ngspice |